Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable primitives that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable resources are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
The function of the FPGA may be altered when the state of certain memory cells is affected by cosmic radiation and the byproducts of radioactive decay. Because the effects of cosmic radiation may increase with increasing altitude, applications for FPGAs at high altitudes and in outer space may be especially vulnerable.
Triple modular redundancy (TMR) may be employed to protect against the unexpected alteration of data stored in FPGA memory cells. With TMR, the design implemented in the programmable logic and interconnect is triplicated and voting circuits are added to compare and determine a correct output from the three outputs of the triplicated logic. The TMRTool from Xilinx, for example, provides the capability to automatically generate TMR for an input design that is targeted to an FPGA.
Programmable logic and interconnect have been configured to implement a processor in combination with BRAM resources implementing the addressable memory for the processor. Program instructions may be stored in the BRAM and fetched and executed by the processor. The MicroBlaze processor implementation from Xilinx, Inc. is an example of such an arrangement. The implementation of a processor on programmable logic and interconnect resources of an FPGA is sometimes referred to as a “soft processor.”
TMR may also be applied to systems having one or more soft processors in combination with other application-specific logic implemented on the programmable logic and interconnect resource of an FPGA. For such a system, the TMRTool may be used to triplicate each processor and BRAM instance and instantiate the appropriate voting circuitry. This implementation may consume a very large portion of FPGA resources, however.
FPGA architectures have evolved to include one or more hard-wired processors on the same chip as the programmable logic and interconnect resources. For example, FPGAs from Xilinx may include one or more PowerPC® processors that are hardwired into the chip (a “hard processor”). That is, the functions of the hard processor are not implemented using the programmable logic and interconnect resources of the FPGA.
Use of TMR with a system that is implemented using both the hard processor and programmable logic and interconnect resources of an FPGA may be problematic. Since there are only a finite number of hard processors available on an FPGA, triplicating the hard processors may not be possible. Also, tools such as the TMRTool may not recognize how to deal with hard processors in a TMR context.
The present invention may address one or more of the above issues.